(a) Field of the Invention
The present invention relates to a semiconductor device having a semiconductor chip suited to a multi-chip package structure.
(b) Description of the Related Art
In recent years, for achieving smaller dimensions for an electronic equipment such as portable data assistant and digital camera, electronic components mounted therein are requested to have higher mounting densities. For achieving a higher mounting density in the thickness direction of the electronic equipment in particular, it is desired to reduce the thickness of semiconductor chips.
In one example of conventional techniques for reducing the thickness of a semiconductor chip, the process includes the steps of fabricating semiconductor transistor elements, interconnections, interlevel dielectric films and a protective film on a wafer, mechanically grinding the bottom surface of the resultant wafer to a desired thickness thereof, and dividing the wafer into a plurality of semiconductor chips having the desired thickness.
However, the mechanical grinding process significantly reduces the mechanical strength of the wafer. The factors of reduction of the mechanical strength of the wafer includes a reduced thickness of the wafer and mechanical damages such as scratches formed on the bottom surface of the wafer during the mechanical grinding process. The damage on the bottom surface may eventually grow and enter the internal of the wafer to form a crack therein. The damages on the bottom surface of the wafer, which reduce the mechanical strength of the semiconductor chip, reduce the product yield of the semiconductor chips divided from the wafer.
A technique for improving the mechanical strength of the wafer is described in, for example, Patent Publication JP-A-2000-124177, wherein the entire bottom surface of the wafer is polished with a finer degree of polishing to remove the damages formed on the bottom surface during the preceding mechanical grinding process.
In general, a process for forming a multi-chip package structure including a plurality of stacked chips uses the technique as described above, wherein each chip is polished to a thickness as small as 100 micrometers (μm) or less, for example.
The technique described in the patent publication improves the mechanical strength of the resultant semiconductor chips. However, there arises another problem wherein the semiconductor chip manufactured using the above technique suffers from degradation of characteristics of transistor elements in the semiconductor chip. The degradation of the characteristic is considered to occur in the manner as described below.
The mechanical grinding on the bottom surface of the wafer allows a minute amount of heavy metals to be attached onto the bottom surface. The heavy metals thus attached are scarcely removed by the succeeding polishing. According to the experiments conducted by the present inventors revealed that the copper attached onto the bottom surface of the wafer after the mechanical grinding process could be reduced only by an amount of 1×1011 atoms/cm2 at most after the succeeding polishing, to leave a significant amount of heavy metals on the bottom surface. The problem caused by the heavy metals occurs in the packaging process for the semiconductor chip.
The packaging process for fabricating the semiconductor package from the semiconductor chip will be described with reference to a lead-on-chip (LOC) type thin-film-outline-package (TSOP). First, a set of leads attached with a LOC tape is bonded onto a semiconductor chip, the LOC tape including an insulation sheet coated with resin on both surfaces thereof. Subsequently, these leads and the electrodes on the semiconductor chip are connected together via bonding wires by using a wire bonding technique. The semiconductor chip, wires and leads are then encapsulated in thermo-setting resin for packaging. The packaging step includes a baking treatment for curing the resin on the LOC tape at a temperature of 150 degrees C. for 30 hours and at a temperature of 230 degrees C. for 90 minutes, and another baking treatment for curing the package resin at a temperature of 180 degrees C. for several tens of minutes to several hours.
The baking treatments, or heat treatments, allow the heavy metals attached onto the bottom surface of the semiconductor chip to diffuse into the internal of the chip. Copper having a highest diffusion rate among the heavy metals attached onto the chip diffuses within the internal of the chip along a distance of several hundreds of micrometers during the heat treatments. This means that the heavy metals such as copper attached onto the bottom surface of the silicon substrate may reach the top surface of the chip during the heat treatments in the packaging step. The heavy metals, if reaches the active layer of the transistors formed in the vicinity of the top surface of the semiconductor chip, degrade the transistor characteristics in the chip.
Assuming that the semiconductor chip is a DRAM chip, for example, the heavy metal reaching depletion layers of the source/drain regions configures an impurity level within the energy bandgap to generate a junction leakage current. A higher junction leakage current degrades the refreshing characteristic of memory cells in the DRAM chip.
It is noted here that in the semiconductor chip manufactured by the conventional process including the mechanical grinding step without a subsequent polishing step, the damages such as scratches formed on the bottom surface of the semiconductor chip have a function of gettering the heavy metals therein. More specifically, the damages suppress the heavy metals from diffusing within the semiconductor chip during the heat treatments in the packaging process by the gettering function thereof.
Thus, it will be understood that the polishing treatment for removing the mechanical damages, if conducted after the grinding treatment, improves the mechanical strength of a semiconductor chip having a small thickness and yet degrades the transistor characteristics. On the contrary, the damages, if they are left after the grinding treatment without effecting the polishing treatment, suppress degradation of the transistor characteristics and yet degrades the mechanical strength. In short, the improvement of mechanical strength and the suppression of degradation of the transistor characteristics are trade-offs in a thin semiconductor chip used in a multi-chip package structure.